[Bug target/93069] Assembler messages: Error: unsupported masking for `vextracti32x8'

[jakub at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93069

--- Comment #3 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
Note, the above isn't the smallest possible fix, so perhaps for backporting
instead of the gcc/config/i386/ changes
--- gcc/config/i386/sse.md.jj   2019-12-27 18:16:48.146431083 +0100
+++ gcc/config/i386/sse.md      2019-12-28 16:54:09.536217497 +0100
@@ -8782,7 +8782,8 @@ (define_expand "avx_vextractf128<mode>"
 })

 (define_insn "vec_extract_lo_<mode><mask_name>"
-  [(set (match_operand:<ssehalfvecmode> 0 "nonimmediate_operand" "=v,v,m")
+  [(set (match_operand:<ssehalfvecmode> 0 "<store_mask_predicate>"
+                                         "=v,v,<store_mask_constraint>")
        (vec_select:<ssehalfvecmode>
          (match_operand:V16FI 1 "<store_mask_predicate>"
                                 "v,<store_mask_constraint>,v")
@@ -8834,7 +8835,8 @@ (define_split
 })

 (define_insn "vec_extract_lo_<mode><mask_name>"
-  [(set (match_operand:<ssehalfvecmode> 0 "<store_mask_predicate>" "=v,v,m")
+  [(set (match_operand:<ssehalfvecmode> 0 "<store_mask_predicate>"
+                                         "=v,v,<store_mask_constraint>")
        (vec_select:<ssehalfvecmode>
          (match_operand:VI8F_256 1 "<store_mask_predicate>"
                                    "v,<store_mask_constraint>,v")
@@ -8844,7 +8846,7 @@ (define_insn "vec_extract_lo_<mode><mask
    && (<mask_applied> || !(MEM_P (operands[0]) && MEM_P (operands[1])))"
 {
   if (<mask_applied>)
-    return "vextract<shuffletype>64x2\t{$0x0, %1, %0%{%3%}|%0%{%3%}, %1,
0x0}";
+    return "vextract<shuffletype>64x2\t{$0x0, %1,
%0<mask_operand2>|%0<mask_operand2>, %1, 0x0}";
   else
     return "#";
 }
might be better, i.e. insist on _maskm patterns for masked operations into
memory and force non-memory destination for the rest of vector extractions,
plus the %{%3%} instead of <mask_operand2> I think can't work properly if zero
masking is needed into register destination.