[Bug rtl-optimization/90001] Compile-time hog in swing modulo scheduler

[zhroma at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90001

--- Comment #6 from Roman Zhuykov <zhroma at gcc dot gnu.org> ---
Author: zhroma
Date: Fri Dec 13 17:02:53 2019
New Revision: 279375

URL: https://gcc.gnu.org/viewcvs?rev=279375&root=gcc&view=rev
Log:
modulo-sched: speed up DDG analysis (PR90001)

        PR rtl-optimization/90001
        * ddg.c (create_ddg): Init max_dist array for each node.
        (free_ddg): Free max_dist array.
        (create_ddg_edge): Use bool field instead of aux union.
        (set_recurrence_length): Use prepared max_dist information instead
        of calling longest_simple_path.
        (create_scc): Remove graph argument, fill node's aux.count with
        SCC id, and move set_recurrence_length call to...
        (create_ddg_all_sccs): ...here, after filling all max_dist arrays
        using Floyd–Warshall-like algorithm.
        (update_dist_to_successors): Remove the whole function.
        (longest_simple_path): Likewise.
        * ddg.h (struct ddg_node): Add max_dist pointer.
        (struct ddg_edge): Use bool field instead of unused aux union.

Modified:
    trunk/gcc/ChangeLog
    trunk/gcc/ddg.c
    trunk/gcc/ddg.h