[Bug target/78176] [MIPS] miscompiles ldxc1 with large pointers on 32-bits

[patrickdepinguin at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78176

--- Comment #31 from Thomas De Schampheleire <patrickdepinguin at gmail dot com> ---
(In reply to Maciej W. Rozycki from comment #27)
> Yes, it is the same problem, the same address calculation occurs here,
> and the lack of 32-bit address space wraparound is a part of the n32
> Linux ABI, which implies support for processors that do not support such
> a wraparound in hardware (no CP0.Status.PX bit).
> 
> You may try experimenting with ISA/ASE selection options, so that LWX is
> not considered a valid instruction by GCC.  Otherwise I can't help with
> finding a workaround as I don't know one offhand and I'm not involved
> with MIPS development anymore, sorry.  And neither is Doug BTW.
> 
> This really ought to be fixed properly in GCC.

I'm currently using -march=octeon3   or -march=octeon2  as appropriate.
I'm not really confident in changing this, as there will be other impact too.

As a quick workaround/test, I will try letting the '-mno-lxc1-sxc1' flag also
control the use of the lwx and similar instructions, as follows:

diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 23e1672b586..5dee3fbe29f 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -1194,17 +1194,17 @@ struct mips_cpu_info {

 /* ISA has lwxs instruction (load w/scaled index address.  */
 #define ISA_HAS_LWXS           ((TARGET_SMARTMIPS || TARGET_MICROMIPS) \
-                                && !TARGET_MIPS16)
+                                && !TARGET_MIPS16 && mips_lxc1_sxc1)

 /* ISA has lbx, lbux, lhx, lhx, lhux, lwx, lwux, or ldx instruction. */
-#define ISA_HAS_LBX            (TARGET_OCTEON2)
-#define ISA_HAS_LBUX           (ISA_HAS_DSP || TARGET_OCTEON2)
-#define ISA_HAS_LHX            (ISA_HAS_DSP || TARGET_OCTEON2)
-#define ISA_HAS_LHUX           (TARGET_OCTEON2)
-#define ISA_HAS_LWX            (ISA_HAS_DSP || TARGET_OCTEON2)
-#define ISA_HAS_LWUX           (TARGET_OCTEON2 && TARGET_64BIT)
+#define ISA_HAS_LBX            (TARGET_OCTEON2 && mips_lxc1_sxc1)
+#define ISA_HAS_LBUX           ((ISA_HAS_DSP || TARGET_OCTEON2) &&
mips_lxc1_sxc1)
+#define ISA_HAS_LHX            ((ISA_HAS_DSP || TARGET_OCTEON2) &&
mips_lxc1_sxc1)
+#define ISA_HAS_LHUX           (TARGET_OCTEON2 && mips_lxc1_sxc1)
+#define ISA_HAS_LWX            ((ISA_HAS_DSP || TARGET_OCTEON2) &&
mips_lxc1_sxc1)
+#define ISA_HAS_LWUX           (TARGET_OCTEON2 && TARGET_64BIT &&
mips_lxc1_sxc1)
 #define ISA_HAS_LDX            ((ISA_HAS_DSP || TARGET_OCTEON2) \
-                                && TARGET_64BIT)
+                                && TARGET_64BIT && mips_lxc1_sxc1)

 /* The DSP ASE is available.  */
 #define ISA_HAS_DSP            (TARGET_DSP && !TARGET_MIPS16)