[Bug middle-end/18041] OR of two single-bit bitfields is inefficient

rguenth at gcc dot gnu.org gcc-bugzilla@gcc.gnu.org
Mon Nov 5 14:22:00 GMT 2018


https://gcc.gnu.org/bugzilla/show_bug.cgi?id=18041

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |segher at gcc dot gnu.org

--- Comment #9 from Richard Biener <rguenth at gcc dot gnu.org> ---
Looks like combine doesn't want

(insn 11 10 13 2 (parallel [
            (set (reg:QI 91)
                (ior:QI (mem/c:QI (plus:SI (reg/f:SI 16 argp)
                            (const_int 4 [0x4])) [4 x+0 S1 A32])
                    (reg:QI 90 [ *b_3(D) ])))
            (clobber (reg:CC 17 flags))
        ]) "t.c":12:11 429 {*iorqi_1}
     (expr_list:REG_UNUSED (reg:CC 17 flags)
        (nil)))

for a combination (on x86_64 with -m32).

(insn 13 11 15 2 (parallel [
            (set (reg:QI 93)
                (and:QI (reg:QI 91)
                    (const_int 1 [0x1])))
            (clobber (reg:CC 17 flags))
        ]) "t.c":12:11 396 {*andqi_1}
     (expr_list:REG_UNUSED (reg:CC 17 flags)
        (expr_list:REG_DEAD (reg:QI 91)
            (nil))))
(insn 15 13 16 2 (parallel [
            (set (reg:QI 95)
                (and:QI (reg:QI 90 [ *b_3(D) ])
                    (const_int -2 [0xfffffffffffffffe])))
            (clobber (reg:CC 17 flags))
        ]) "t.c":12:11 396 {*andqi_1}
     (expr_list:REG_DEAD (reg:QI 90 [ *b_3(D) ])
        (expr_list:REG_UNUSED (reg:CC 17 flags)
            (nil))))
(insn 16 15 17 2 (parallel [
            (set (reg:QI 96)
                (ior:QI (reg:QI 95)
                    (reg:QI 93)))
            (clobber (reg:CC 17 flags))
        ]) "t.c":12:11 429 {*iorqi_1}
     (expr_list:REG_DEAD (reg:QI 95)
        (expr_list:REG_DEAD (reg:QI 93)
            (expr_list:REG_UNUSED (reg:CC 17 flags)
                (nil)))))

Trying 11, 15, 13 -> 16:
   11: {r91:QI=[argp:SI+0x4]|r90:QI;clobber flags:CC;}
      REG_UNUSED flags:CC
   15: {r95:QI=r90:QI&0xfffffffffffffffe;clobber flags:CC;}
      REG_DEAD r90:QI
      REG_UNUSED flags:CC
   13: {r93:QI=r91:QI&0x1;clobber flags:CC;}
      REG_UNUSED flags:CC
      REG_DEAD r91:QI
   16: {r96:QI=r95:QI|r93:QI;clobber flags:CC;}
      REG_DEAD r95:QI
      REG_DEAD r93:QI
      REG_UNUSED flags:CC
Failed to match this instruction:
(parallel [
        (set (reg:QI 96)
            (ior:QI (and:QI (mem/c:QI (plus:SI (reg/f:SI 16 argp)
                            (const_int 4 [0x4])) [4 x+0 S1 A32])
                    (const_int 1 [0x1]))
                (reg:QI 90 [ *b_3(D) ])))
        (clobber (reg:CC 17 flags))
    ])
Failed to match this instruction:
(set (reg:QI 96)
    (ior:QI (and:QI (mem/c:QI (plus:SI (reg/f:SI 16 argp)
                    (const_int 4 [0x4])) [4 x+0 S1 A32])
            (const_int 1 [0x1]))
        (reg:QI 90 [ *b_3(D) ])))
Failed to match this instruction:
(set (reg:QI 95)
    (and:QI (mem/c:QI (plus:SI (reg/f:SI 16 argp)
                (const_int 4 [0x4])) [4 x+0 S1 A32])
        (const_int 1 [0x1])))

looks like it doesn't try to "factor" out the load?


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