[Bug target/83009] gcc.target/aarch64/store_v2vec_lanes.c fails with -mabi=ilp32

[avieira at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83009

--- Comment #8 from avieira at gcc dot gnu.org ---
Author: avieira
Date: Thu May 24 08:53:39 2018
New Revision: 260635

URL: https://gcc.gnu.org/viewcvs?rev=260635&root=gcc&view=rev
Log:
PR target/83009: Relax strict address checking for store pair lanes

The operand constraint for the memory address of store/load pair lanes was
enforcing strictly hardware registers be allowed as memory addresses.  We want
to relax that such that these patterns can be used by combine.  During register
allocation the register constraint will enforce the correct register is chosen.

gcc
2018-05-24  Andre Vieira  <andre.simoesdiasvieira@arm.com>

        PR target/83009
        * config/aarch64/predicates.md (aarch64_mem_pair_lanes_operand): Make
        address check not strict.

gcc/testsuite
2018-05-24  Andre Vieira  <andre.simoesdiasvieira@arm.com>

        PR target/83009
        * gcc/target/aarch64/store_v2vec_lanes.c: Add extra tests.

Modified:
    trunk/gcc/ChangeLog
    trunk/gcc/config/aarch64/predicates.md
    trunk/gcc/testsuite/ChangeLog
    trunk/gcc/testsuite/gcc.target/aarch64/store_v2vec_lanes.c