[Bug target/85073] New: [x86] extra check after BLSR

[wojciech_mula at poczta dot onet.pl]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85073

            Bug ID: 85073
           Summary: [x86] extra check after BLSR
           Product: gcc
           Version: 7.3.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: wojciech_mula at poczta dot onet.pl
  Target Milestone: ---

GCC is able to use the BLSR instruction in place of expression (x - 1) & x
[which is REALLY nice, thank you :)], but does not utilize CPU flags set by the
instruction. Below is a simple example.

--bmi1.c--
int popcount(unsigned x) {
    int c = 0;
    while (x) {
        c += 1;
        x = (x - 1) & x;
    }

    return c;
}
--eof--

$ gcc --version
gcc (Debian 7.3.0-11) 7.3.0

$ gcc -march=skylake -O3 -s bmi1.c && cat bmi1.s

popcount:
.LFB0:
        xorl    %eax, %eax
        testl   %edi, %edi
        je      .L4
.L3:
        addl    $1, %eax
        blsr    %edi, %edi <<< HERE
        testl   %edi, %edi <<< and HERE
        jne     .L3
        ret
.L4:
        ret

BLSR sets the ZF flag if the result is zero. The subsequent TEST instruction is
not needed.