[Bug middle-end/80283] [6/7/8 Regression] bad SIMD register allocation

[rsandifo at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80283

--- Comment #24 from rsandifo at gcc dot gnu.org <rsandifo at gcc dot gnu.org> ---
(In reply to Wilco from comment #23)
> (In reply to rsandifo@gcc.gnu.org from comment #22)
> 
> > > SCHED_PRESSURE_MODEL first tries to create a "model" schedule
> > > that keeps register down as far as possible and then uses that
> > > to guide the "real" schedule.  It looks like the model schedule
> > > goes catastrophically wrong in this case though: the original
> > > order had a VFP_REGS pressure of 56 (against a capacity of 64)
> > > while the model schedule had a pressure of 76(!).
> 
> Since when does ARM have 64 128-bit VFP registers? If it can't even count
> registers correctly that's the #1 problem right there...

Each 32-bit chunk is modelled as a separate VFP register, and 128-bit
modes take 4 registers each, so it all works out.