[Bug target/85769] [8/9 Regression] ICE in extract_constrain_insn, at recog.c:2205 for -mcpu=thunderx

[tnfchris at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85769

--- Comment #5 from Tamar Christina <tnfchris at gcc dot gnu.org> ---
Author: tnfchris
Date: Wed Jun 27 08:08:48 2018
New Revision: 262178

URL: https://gcc.gnu.org/viewcvs?rev=262178&root=gcc&view=rev
Log:
Add SIMD to REG pattern for movhf without armv8.2-a support for AArch64

This fixes a regression where we don't have an instruction for pre Armv8.2-a
to do a move of an fp16 value from a GP reg to a SIMD reg.

This patch adds that pattern to movhf_aarch64 using a dup and only selectes it
using a very low priority.

This fixes an ICE at -O0.

gcc/
2018-06-20  Tamar Christina  <tamar.christina@arm.com>

        PR target/85769
        * config/aarch64/aarch64.md (*movhf_aarch64): Add dup v0.4h pattern.

gcc/testsuite/
2018-06-20  Tamar Christina  <tamar.christina@arm.com>

        PR target/85769
        * gcc.target/aarch64/f16_mov_immediate_3.c: New.


Added:
    trunk/gcc/testsuite/gcc.target/aarch64/f16_mov_immediate_3.c
Modified:
    trunk/gcc/ChangeLog
    trunk/gcc/config/aarch64/aarch64.md
    trunk/gcc/testsuite/ChangeLog