[Bug target/82303] Better PIE/PIC code generation for kernel code (x86_64 & arm64)
thgarnie at google dot com
gcc-bugzilla@gcc.gnu.org
Fri Jan 19 18:57:00 GMT 2018
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82303
--- Comment #9 from Thomas Garnier <thgarnie at google dot com> ---
I tested the change against a modified version of the proposed Linux x86_64 PIE
support. The changes removes all the PLT32 and GOT64 entry but I still get
R_X86_64_GOTPC64 & R_X86_64_GOTOFF64 relocations on the head64.c file that is
built with -mcmodel=large (to prevent odd logic on early boot with different
VA).
Do you think the suggested patch can be changed to remove these?
To repro, build the object file with: gcc -mcmodel=large -c -fstatic-pie
./test.c -o test
The objdump -dr output of the testcase:
0000000000000000 <main>:
0: 55 push %rbp
1: 48 89 e5 mov %rsp,%rbp
4: 48 83 ec 20 sub $0x20,%rsp
8: 48 8d 05 f9 ff ff ff lea -0x7(%rip),%rax # 8 <main+0x8>
f: 49 bb 00 00 00 00 00 movabs $0x0,%r11
16: 00 00 00
11: R_X86_64_GOTPC64 _GLOBAL_OFFSET_TABLE_+0x9
19: 4c 01 d8 add %r11,%rax
1c: 89 7d ec mov %edi,-0x14(%rbp)
1f: 48 89 75 e0 mov %rsi,-0x20(%rbp)
23: 48 ba 00 00 00 00 00 movabs $0x0,%rdx
2a: 00 00 00
25: R_X86_64_GOTOFF64 _text-0x1023
2d: 48 8d 14 10 lea (%rax,%rdx,1),%rdx
31: 89 55 fc mov %edx,-0x4(%rbp)
34: 8b 55 ec mov -0x14(%rbp),%edx
37: 48 63 d2 movslq %edx,%rdx
3a: 48 8b 4d e0 mov -0x20(%rbp),%rcx
3e: 48 89 ce mov %rcx,%rsi
41: 48 b9 00 00 00 00 00 movabs $0x0,%rcx
48: 00 00 00
43: R_X86_64_GOTOFF64 _text
4b: 48 8d 3c 08 lea (%rax,%rcx,1),%rdi
4f: 48 b9 00 00 00 00 00 movabs $0x0,%rcx
56: 00 00 00
51: R_X86_64_GOTOFF64 memcpy
59: 48 8d 04 08 lea (%rax,%rcx,1),%rax
5d: ff d0 callq *%rax
5f: 8b 45 fc mov -0x4(%rbp),%eax
62: c9 leaveq
63: c3 retq
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