[Bug target/83399] Power8 ICE During LRA with 2-op rtl pattern for lvx instruction

[bergner at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83399

--- Comment #13 from Peter Bergner <bergner at gcc dot gnu.org> ---
Author: bergner
Date: Wed Jan 10 20:49:36 2018
New Revision: 256453

URL: https://gcc.gnu.org/viewcvs?rev=256453&root=gcc&view=rev
Log:
gcc/
        PR target/83399
        * config/rs6000/rs6000.c (print_operand) <'y'>: Use
        VECTOR_MEM_ALTIVEC_OR_VSX_P.
        * config/rs6000/vsx.md (*vsx_le_perm_load_<mode> for VSX_D): Use
        indexed_or_indirect_operand predicate.
        (*vsx_le_perm_load_<mode> for VSX_W): Likewise.
        (*vsx_le_perm_load_v8hi): Likewise.
        (*vsx_le_perm_load_v16qi): Likewise.
        (*vsx_le_perm_store_<mode> for VSX_D): Likewise.
        (*vsx_le_perm_store_<mode> for VSX_W): Likewise.
        (*vsx_le_perm_store_v8hi): Likewise.
        (*vsx_le_perm_store_v16qi): Likewise.
        (eight unnamed splitters): Likewise.

gcc/testsuite/
        PR target/83399
        * gcc.target/powerpc/pr83399.c: New test.

Added:
    trunk/gcc/testsuite/gcc.target/powerpc/pr83399.c
Modified:
    trunk/gcc/ChangeLog
    trunk/gcc/config/rs6000/rs6000.c
    trunk/gcc/config/rs6000/vsx.md
    trunk/gcc/testsuite/ChangeLog