[Bug target/83399] Power8 ICE During LRA with 2-op rtl pattern for lvx instruction

[vmakarov at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83399

--- Comment #9 from Vladimir Makarov <vmakarov at gcc dot gnu.org> ---
(In reply to Peter Bergner from comment #8)
> Created attachment 43064 [details]
> Proposed fix
> 
> I'm testing the attached patch.

Thank you, Peter.  I thought about resurrection of address mutations (e.g. AND)
in LRA.  But I would definitely prefer your approach as it is
machine-dependent, does not affect other targets, and less complicated than my
approach.