[Bug rtl-optimization/83565] [7/8 regression] RTL combine pass breaks shift result (at least on ia64)

[law at redhat dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83565

Jeffrey A. Law <law at redhat dot com> changed:

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--- Comment #27 from Jeffrey A. Law <law at redhat dot com> ---
WORD_REGISTER_OPERATIONS says the operations in integral modes smaller than a
word are performed on the entire register (ie a word).

I think WORD_REGISTER_OPERATIONS is fairly intuitive when it comes to
arithmetic and logicals. For arith/logicals I would find myself agreeing with
Eric in c#25.

However, I think it's not as clear for shifts/rotates.

On the PA (which defines WORD_REGISTER_OPERATIONS) we have 32bit
deposit/extract  which are used for various shifts.  The 32bit extract/deposit
instructions set the low 32 bits in the expected way, but leave the upper bits
undefined.  So I suspect PA and IA-64 have similar behavior (big surprise).

One could argue that WORD_REGISTER_OPERATIONS should apply to just arith and
logicals.  One could also argue that it should apply to shifts in which case
ports like the PA and IA-64 probably shouldn't define WORD_REGISTER_OPERATIONS.

If we were to argue that WORD_REGISTER_OPERATIONS should apply to just
arith/logicals, then the PA would need to be audited for cases where we might
implement an arith operation using shifts (deposit/extract instructions).

And just to be clear here.  I don't think the PA or IA-64 ought to drive
decisions in this area.  They're both dead architectures -- but others may have
similar properties.


Note none of this touches on what are the high bits of a paradoxical subreg,
which are undefined in RTL.  So I'm in partial agreement with Jim c#11 as well.