[Bug rtl-optimization/84071] [7/8 regression] wrong elimination of zero-extension after sign-extended load

[ebotcazou at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84071

--- Comment #20 from Eric Botcazou <ebotcazou at gcc dot gnu.org> ---
> How is this any different from 32-bit operations in say MIPS? The only
> difference seems to be that MIPS sign-extends 32-bit operations to 64 bit
> while AArch64 zero-extends. If that's correct for MIPS it seems that
> WORD_REGISTER_OPERATIONS only applies to types smaller than SImode.

Interesting question.  One indeed could argue that, if 64-bit MIPS defines it,
then Aarch64 could do it too since they are symmetric wrt sign/zero-extension
but I don't have a definitive answer as I don't really know the history of
WORD_REGISTER_OPERATIONS on MIPS.  Maybe worth a try if this brings measurable
benefits, typically elimination of redundant 32->64 zero-extensions.