[Bug target/81357] Extra mov for zero extend of add

[qing.zhao at oracle dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81357

--- Comment #8 from Qing Zhao <qing.zhao at oracle dot com> ---
> 
> I don't think there is an easy fix for this example. The compiler believes
> there are 2 distinct values so it uses 2 registers irrespectively of the order
> of the mov and uxtw.

then, why when there is NO -fschedule-insns, i.e, when compiled with -O, the
assembly
does not have the additional “mov” insn:
***/home/qinzhao/Install/latest/bin/gcc -O t.c
test1:
        add     w0, w0, 1
        uxtw    x2, w0
        adrp    x1, d
        str     x2, [x1, #:lo12:d]
        ret