[Bug tree-optimization/71307] Poor code quality with lane extraction arm_neon.h intrinsics on aarch64

[rsandifo at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71307

--- Comment #7 from rsandifo at gcc dot gnu.org <rsandifo at gcc dot gnu.org> ---
Author: rsandifo
Date: Mon Oct  2 08:11:07 2017
New Revision: 253337

URL: https://gcc.gnu.org/viewcvs?rev=253337&root=gcc&view=rev
Log:
[AArch64] PR71307: Define union class of POINTER+FP

ALL_REGS doesn't function as a union class of POINTER_REGS and FP_REGS
since it includes the CC register as well.  REGNO_REG_CLASS (CC_REGNUM)
is NO_REGS, but of course NO_REGS rightly doesn't include CC_REGNUM.

Adding a union class for POINTER+FP allows the RA to use it as the
preferred or alternative class of a pseudo.  It also works as a
union class of GENERAL+FP for modes that aren't allowed in SP.

This is also needed for the SVE port, which adds predicate registers
to the mix.

2017-09-15  Richard Sandiford  <richard.sandiford@linaro.org>
            Alan Hayward  <alan.hayward@arm.com>
            David Sherwood  <david.sherwood@arm.com>

gcc/
        PR target/71307
        * config/aarch64/aarch64.h (POINTER_AND_FP_REGS): New reg class.
        (REG_CLASS_NAMES, REG_CLASS_CONTENTS): Update accordingly.
        * config/aarch64/aarch64.c (aarch64_class_max_nregs): Handle
        POINTER_AND_FP_REGS.

gcc/testsuite/
        PR target/71307
        * gcc.target/aarch64/vect_copy_lane_1.c: Remove XFAIL.

Modified:
    trunk/gcc/ChangeLog
    trunk/gcc/config/aarch64/aarch64.c
    trunk/gcc/config/aarch64/aarch64.h
    trunk/gcc/testsuite/ChangeLog
    trunk/gcc/testsuite/gcc.target/aarch64/vect_copy_lane_1.c