[Bug target/82931] New: Missing Optimization for Bit-Transfer (AVR Target)

wilhelm.meier@hs-kl.de gcc-bugzilla@gcc.gnu.org
Fri Nov 10 08:00:00 GMT 2017


https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82931

            Bug ID: 82931
           Summary: Missing Optimization for Bit-Transfer (AVR Target)
           Product: gcc
           Version: 8.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: wilhelm.meier@hs-kl.de
  Target Milestone: ---

Created attachment 42574
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=42574&action=edit
Minimum complete verifying example

The attached example produces optimal code for the AVR-target: it uses the
bst/bld assembler instructions. But this is only true for bit 0 (least
significant) in an uint8_t type. If the same instruction sequence is used to
transfer bit 1...7 less optimal code is generated.

This is unlogical to some respect since the backend recognizes the special case
for bit 0, so it should be possible to use the very same optimization for other
bits.

The same holds true if one used another datatype such as uint16_t and greater.
No optimization takes place.


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