[Bug target/54168] ARM: Redundant instructions emitted at -O3

[wilco at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=54168

Wilco <wilco at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|NEW                         |RESOLVED
                 CC|                            |wilco at gcc dot gnu.org
      Known to work|                            |6.3.1
         Resolution|---                         |FIXED
      Known to fail|                            |4.8.2, 5.4.1

--- Comment #3 from Wilco <wilco at gcc dot gnu.org> ---
(In reply to Mans Rullgard from comment #0)
> Created attachment 27932 [details]
> Test case
> 
> Compiling the attached code for ARM results in redundant instructions even
> at -O3 optimisation.  Note this sequence (interleaved with other
> instructions):
> 
>         ldrh    r3, [r0]        @ unaligned
>         and     r3, r3, #2
>         uxth    r3, r3
>         cmp     r3, #0
>         beq     .L2
> 
> The UXTH is clearly redundant since no more than 16 bits can be set by LDRH.
> Once this is removed, the CMP can be folded with the AND as ANDS.
> 
> Interestingly, this badness only happens with -march=armv6 or higher.  If
> the target is v5, sane code is generated.
> 
> This is a regression in the 4.7 and 4.8 branches.  4.6 and earlier behave
> properly.

GCC6.3 produces with -O3:

        ldrh    r0, [r1]
        ands    r0, r0, #2
        it      ne
        movne   r0, #0
        beq     .L8

Closing as GCC4.8 isn't active.