[Bug rtl-optimization/80425] Extra inter-unit register move with zero-extension

[ubizjak at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80425

--- Comment #5 from Uroš Bizjak <ubizjak at gmail dot com> ---
Author: uros
Date: Mon May 15 19:04:35 2017
New Revision: 248070

URL: https://gcc.gnu.org/viewcvs?rev=248070&root=gcc&view=rev
Log:
        * config/i386.i386.md (*zero_extendsidi2): Do not penalize
        non-interunit SSE move alternatives with '?'.
        (zero-extendsidi peephole2): New peephole to skip intermediate
        general register in SSE zero-extend sequence.

testsuite/ChangeLog:

        * gcc.target/i386/pr80425-1.c: New test.
        * gcc.target/i386/pr80425-2.c: Ditto.


Added:
    trunk/gcc/testsuite/gcc.target/i386/pr80425-1.c
    trunk/gcc/testsuite/gcc.target/i386/pr80425-2.c
Modified:
    trunk/gcc/ChangeLog
    trunk/gcc/config/i386/i386.md
    trunk/gcc/testsuite/ChangeLog