[Bug target/68163] GCC on power8 does not issue the stxsspx instruction on power8

[meissner at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68163

--- Comment #3 from Michael Meissner <meissner at gcc dot gnu.org> ---
Author: meissner
Date: Tue May  9 21:25:23 2017
New Revision: 247819

URL: https://gcc.gnu.org/viewcvs?rev=247819&root=gcc&view=rev
Log:
[gcc]
2017-05-09  Michael Meissner  <meissner@linux.vnet.ibm.com>

        PR target/68163
        * config/rs6000/rs6000.md (f32_lr): Delete mode attributes that
        are now unused after splitting mov{sf,sd}_hardfloat.
        (f32_lr2): Likewise.
        (f32_lm): Likewise.
        (f32_lm2): Likewise.
        (f32_li): Likewise.
        (f32_li2): Likewise.
        (f32_lv): Likewise.
        (f32_sr): Likewise.
        (f32_sr2): Likewise.
        (f32_sm): Likewise.
        (f32_sm2): Likewise.
        (f32_si): Likewise.
        (f32_si2): Likewise.
        (f32_sv): Likewise.
        (f32_dm): Likewise.
        (f32_vsx): Likewise.
        (f32_av): Likewise.
        (mov<mode>_hardfloat): Split into separate movsf and movsd pieces.
        For movsf, order stores so the VSX stores occur before the GPR
        store which encourages the register allocator to use a traditional
        FPR instead of a GPR.  For movsd, order the stores so that the GPR
        store comes before the VSX stores to allow the power6 to work.
        This is due to the power6 not having a 32-bit integer store
        instruction from a FPR.
        (movsf_hardfloat): Likewise.
        (movsd_hardfloat): Likewise.

[gcc/testsuite]
2017-05-09  Michael Meissner  <meissner@linux.vnet.ibm.com>

        PR target/68163
        * gcc.target/powerpc/pr68163.c: New test.


Added:
    trunk/gcc/testsuite/gcc.target/powerpc/pr68163.c
Modified:
    trunk/gcc/ChangeLog
    trunk/gcc/config/rs6000/rs6000.md
    trunk/gcc/testsuite/ChangeLog