[Bug target/79038] Improve PowerPC ISA 3.0 conversion between integers and hardware _Float128
meissner at gcc dot gnu.org
gcc-bugzilla@gcc.gnu.org
Fri May 5 20:21:00 GMT 2017
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79038
--- Comment #7 from Michael Meissner <meissner at gcc dot gnu.org> ---
Author: meissner
Date: Fri May 5 20:21:15 2017
New Revision: 247657
URL: https://gcc.gnu.org/viewcvs?rev=247657&root=gcc&view=rev
Log:
[gcc]
2017-05-05 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/79038
PR target/79202
PR target/79203
* config/rs6000/rs6000.md (u code attribute): Add FIX and
UNSIGNED_FIX.
(extendsi<mode>2): Add support for doing sign extension via
VUPKHSW and XXPERMDI if the value is in Altivec registers and we
don't have ISA 3.0 instructions.
(extendsi<mode>2 splitter): Likewise.
(fix_trunc<mode>si2): If we are at ISA 2.07 (VSX small integer),
generate the normal insns since SImode can now go in vector
registers. Disallow the special UNSPECs needed for previous
machines to hide SImode being used. Add new insns
fctiw{,w}_<mode>_smallint if SImode can go in vector registers.
(fix_trunc<mode>si2_stfiwx): Likewise.
(fix_trunc<mode>si2_internal): Likewise.
(fixuns_trunc<mode>si2): Likewise.
(fixuns_trunc<mode>si2_stfiwx): Likewise.
(fctiw<u>z_<mode>_smallint): Likewise.
(fctiw<u>z_<mode>_mem): New combiner pattern to prevent conversion
of floating point to 32-bit integer from doing a direct move to
the GPR registers to do a store.
(fctiwz_<mode>): Break long line.
[gcc/testsuite]
2017-05-05 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/79038
PR target/79202
PR target/79203
* gcc.target/powerpc/ppc-round3.c: New test.
* gcc.target/powerpc/ppc-round2.c: Update expected code.
Added:
trunk/gcc/testsuite/gcc.target/powerpc/ppc-round3.c
Modified:
trunk/gcc/ChangeLog
trunk/gcc/config/rs6000/rs6000.md
trunk/gcc/testsuite/ChangeLog
trunk/gcc/testsuite/gcc.target/powerpc/ppc-round2.c
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