[Bug target/69460] ARM Cortex M0 produces suboptimal code vs Cortex M3

[strntydog at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69460

--- Comment #5 from strntydog at gmail dot com ---
I also just calculated the number of cycles each function takes:

Test 1 - 50% More CPU Cycles
Test 2 - 25% More CPU Cycles
Test 3 - 5% More CPU Cycles
Test 4 - 39% More CPU Cycles
Test 5 - 6% More CPU Cycles
Test 6 - 46% More CPU Cycles

This assumes Zero Wait state access to memory, any wait states will make these
differences worse, as the excess cycles are the result of extra flash accesses.

So, even Test 3 and 5 which have the same code size will run ~5% slower than it
should, which is significant.  But the worst cases will be dramatically slower.

This bug leads not only to slower execution, but that has a direct impact on
Power Efficiency and battery life in battery powered devices (which are a
target market for M0/M0+ processors).

These are extremely common and simple memory access patterns, and every single
M0/M0+ program will be negatively effected by it.