[Bug tree-optimization/80155] [7 regression] Performance regression with code hoisting enabled
rguenth at gcc dot gnu.org
gcc-bugzilla@gcc.gnu.org
Tue Mar 28 13:33:00 GMT 2017
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80155
--- Comment #18 from Richard Biener <rguenth at gcc dot gnu.org> ---
(In reply to Thomas Preud'homme from comment #17)
> (In reply to rguenther@suse.de from comment #16)
> > On Thu, 23 Mar 2017, thopre01 at gcc dot gnu.org wrote:
> > >
> > > Funnily this led back to the Cortex-M0+ reduced testcase. With the patch in
> > > comment #13 applied we can still see a difference in the push (one register
> > > pushed Vs 0).
> >
> > I can't reproduce zero pushes here I get three with/without
> > -fno-code-hoisting. code hoisting hoists the two loads inside
> > the switch before it so we have
>
> Ooops my apologize, it needs more flags indeed. -O2 -funroll-all-loops shows
> 2 registers pushed Vs 1 when -fno-code-hoisting is added.
Still can't reproduce. I've configured with
/space/rguenther/src/svn/gcc-7-branch/configure --target=arm-suse-linux-gnueabi
--disable-libstdcxx-pch --enable-languages=c,c++
and am using
./cc1 -quiet cortex-m0plus_reproducer.c -O2 -mcpu=cortex-m0plus -mthumb -I
include -fdump-tree-pre-details -fdump-tree-crited -fdump-tree-all
-funroll-all-loops -fno-code-hoisting
seeing 3 pushes:
fn1:
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
movs r3, #0
push {r4, r5, lr}
I see softfp being used, not sure how I could change that (if that's what I'm
missing). Btw, -funroll-all-loops disqualifies this testcase ;)
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