[Bug tree-optimization/78972] [5/6/7 Regression] poor x86 simd instruction scheduling

law at redhat dot com gcc-bugzilla@gcc.gnu.org
Fri Mar 10 16:00:00 GMT 2017

Previous message (by thread): [Bug tree-optimization/78972] [5/6/7 Regression] poor x86 simd instruction scheduling
Next message (by thread): [Bug target/79185] [5/6/7 Regression] register allocation in the addition of two 128 bit ints
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78972

Jeffrey A. Law <law at redhat dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Target Milestone|7.0                         |8.0

Previous message (by thread): [Bug tree-optimization/78972] [5/6/7 Regression] poor x86 simd instruction scheduling
Next message (by thread): [Bug target/79185] [5/6/7 Regression] register allocation in the addition of two 128 bit ints
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

More information about the Gcc-bugs mailing list