[Bug target/81228] [7/8 Regression] ICE in gen_vec_cmpv2dfv2di, at config/aarch64/aarch64-simd.md:2508

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81228

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |NEW
   Last reconfirmed|                            |2017-06-28
                 CC|                            |amker at gcc dot gnu.org
   Target Milestone|---                         |7.2
            Summary|ICE in gen_vec_cmpv2dfv2di, |[7/8 Regression] ICE in
                   |at                          |gen_vec_cmpv2dfv2di, at
                   |config/aarch64/aarch64-simd |config/aarch64/aarch64-simd
                   |.md:2508                    |.md:2508
     Ever confirmed|0                           |1

--- Comment #1 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
LTGT is not in that switch for some reason.

The definition:
/* This is an ordered NE, ie !UNEQ, ie false for NaN.  */
DEF_RTL_EXPR(LTGT, "ltgt", "ee", RTX_COMM_COMPARE)

The pattern was introduced with:
https://gcc.gnu.org/viewcvs/gcc?view=revision&revision=239327