[Bug rtl-optimization/81434] AArch64 instruction fusing and pipeline scheduling problem

[wilco at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81434

Wilco <wilco at gcc dot gnu.org> changed:

           What    |Removed                     |Added
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                 CC|                            |wilco at gcc dot gnu.org

--- Comment #4 from Wilco <wilco at gcc dot gnu.org> ---
To more accurately schedule fusion pairs wouldn't we need to specify the
scheduling behaviour of the group as well? From the dumps below it schedules
the adrp/add in the same cycle if we're lucky, but it is modelled as using 2
ALUs rather than a new single fused instruction.

Also is your change fixing the issue that the scheduler cannot schedule 2
instructions with a zero latency dependency between them in the same cycle?
That's a very similar bug.