[Bug target/79233] New: portable p-bit shift with p <= 64 not optimized on powerpc64

[vincent-gcc at vinc17 dot net]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79233

            Bug ID: 79233
           Summary: portable p-bit shift with p <= 64 not optimized on
                    powerpc64
           Product: gcc
           Version: 6.3.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: vincent-gcc at vinc17 dot net
  Target Milestone: ---

The srd instruction of powerpc64 appears to support 64-bit shift, the result
being 0 in this case[*]. In ISO C, one would write:

unsigned long shift (unsigned long x, int s)
{
  return s != sizeof (unsigned long) * 8 ? x >> s : 0UL;
}

but the generated code with GCC 6.3.0 (tested on gcc112.fsffrance.org) gives:

shift:
        cmpwi 7,4,64
        beq 7,.L3
        srd 3,3,4
        blr
        .p2align 4,,15
.L3:
        li 3,0
        blr

The test is unnecessary as the branch giving 0 is equivalent.

[*]
http://www.ibm.com/support/knowledgecenter/ssw_aix_61/com.ibm.aix.alangref/idalangref_srd_instrs.htm
"Shift amounts from 64 to 127 give a zero result."