[Bug target/79209] AArch64: Inconsistent packed volatile bitfield accesses

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79209

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Keywords|                            |wrong-code
             Target|                            |aarch64
             Status|UNCONFIRMED                 |NEW
   Last reconfirmed|                            |2017-01-24
          Component|c++                         |target
     Ever confirmed|0                           |1

--- Comment #1 from Richard Biener <rguenth at gcc dot gnu.org> ---
The question is whether a -fstrict-volatile-bitfield volatile bitfield isn't
ill-formed if not properly aligned.  At least for architectures with strict
alignment requirements - aarch has

/* Define this macro to be non-zero if instructions will fail to work
   if given data not on the nominal alignment.  */
#define STRICT_ALIGNMENT                TARGET_STRICT_ALIGN

and -mstrict-align (not sure about the default).  Note this may be very well
a fault of the aarch64 insv/extv patterns (or we may not use those with
-fstrict-volatile-bitfields or their use need to be massaged).

-fstrict-volatile-bitfields should guarantee the access is in SImode in this
case (AFAIR).