[Bug target/78660] [7 Regression] 7.0 bootstrap fail on mips64el-unknow-linux: configure-stage2-target-libgcc' failed

[ebotcazou at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78660

--- Comment #14 from Eric Botcazou <ebotcazou at gcc dot gnu.org> ---
> Yes, that is true but the upper 32-bits still need to be 'zero'. What
> happens later on is that the (subreg:SI (reg:DI 316)) is spilled, spilling
> only 32-bits to the stack but it gets reloaded as DImode/64-bit. The
> upper-32 bits are junk.

Then either the MIPS port is not correctly parameterized, because
LOAD_EXTEND_OP says that the upper 32 bits are *not* junk (see also comment 11)
or...

> I don't believe that is an LRA bug as it is doing exactly what is described by
> the subreg.

...it's a LRA bug if it spills 32 bits but reloads 64 bits; Old Reload knows
that it cannot do that if WORD_REGISTER_OPERATIONS is 1.

So does LRA generate a full 64-bit load or an extended 32-to-64-bit load?