[Bug c/78974] New: STM32L4 CPU read burst access equal to or more than 9 registers to FMC returns corrupted data starting from the 9th read word

[abdullah_khalil at mentor dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78974

            Bug ID: 78974
           Summary: STM32L4 CPU read burst access equal to or more than 9
                    registers to FMC returns corrupted data starting from
                    the 9th read word
           Product: gcc
           Version: unknown
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: c
          Assignee: unassigned at gcc dot gnu.org
          Reporter: abdullah_khalil at mentor dot com
  Target Milestone: ---

I have been working on STM32L486ZG board. There is an issue with the board when
connected to external SRAM using FSMC (Flexible static Memory Controller) as
written in the Errata as follow:

“CPU read burst access equal to or more than 9 registers to FMC returns
corrupted data starting from the 9th read word. These bursts can only be
generated by Cortex®-M4 CPU and not by the other masters (i.e not by DMA).
This issue occurs when the stack is remapped on the external memory on the FMC
and POP operations are performed with 9 or more registers.
This also occurs when LDM/VLDM operations are used with 9 or more registers.”

So we can’t use LDM instructions in this case when executing from external SRAM
in regular cases. For example following instruction will cause an error:
ldmia sp!, {r4,r5,r6,r7,r8,r9,r0,r11,pc}
the value of pc is not restored correctly thus causing an error in the flow.

Is there an optimization present in gcc or some flag present to capture this
issue and limit the number of registers used in one instruction.