[Bug target/79282] [7 Regresion] FAIL: gcc.target/arm/neon-for-64bits-1.c scan-assembler-times vshr 0

[vmakarov at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79282

--- Comment #7 from Vladimir Makarov <vmakarov at gcc dot gnu.org> ---
(In reply to Vladimir Makarov from comment #6)

> I think changing pattern
> 
> &r(1) = 0(2), r(3)
> 
> to
> 
> r(1) = 0(2), r(3)
> 
> would be a right solution on the target side.  The operand 1 can not
> get the same hard register as input operands or other early clobbered
> output operands because it should be the same as operand 2 which
> already can not be assigned to the same hard reg as other input and
> early clobber output operands.
> 
> 
Sorry, It will not work.  I missed the case when operand 2 and 3 is the same
pseudo.  In this case we can not just remove early clobber flag '&'.

OK, I'll try to implement fix in LRA. But it might take 1-2 weeks.