[Bug rtl-optimization/83565] RTL combine pass breaks shift result (at least on ia64)

[ebotcazou at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83565

--- Comment #15 from Eric Botcazou <ebotcazou at gcc dot gnu.org> ---
> Thanks Jim, that makes sense. It seems to me that WORD_REGISTER_OPERATIONS
> should still be true on ia64 given the description in the documentation.

I disagree, WORD_REGISTER_OPERATIONS means that the (general) registers are
always modified as a whole by arithmetic operations.  If that isn't the case,
then the macro should not be defined (e.g Aarch64 doesn't define it although
ARM does).

> This regression was introduced in r242326, which added the `&& !REG_P
> (SUBREG_REG (x))` to nonzero_bits1, thereby assuming that the high bits were
> defined, which is a target-specific assumption.

No, see above, WORD_REGISTER_OPERATIONS means that the bits are defined.