[Bug rtl-optimization/83565] RTL combine pass breaks shift result (at least on ia64)

[jrtc27 at jrtc27 dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83565

James Clarke <jrtc27 at jrtc27 dot com> changed:

           What    |Removed                     |Added
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  Attachment #42961|0                           |1
        is obsolete|                            |

--- Comment #13 from James Clarke <jrtc27 at jrtc27 dot com> ---
Created attachment 42963
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=42963&action=edit
Higher bits of paradoxical subregs on ia64 are undefined

Thanks Jim, that makes sense. It seems to me that WORD_REGISTER_OPERATIONS
should still be true on ia64 given the description in the documentation. This
regression was introduced in r242326, which added the `&& !REG_P (SUBREG_REG
(x))` to nonzero_bits1, thereby assuming that the high bits were defined, which
is a target-specific assumption. The attached patch therefore encodes this
assumption in whether WORD_REGISTER_OPERATIONS is positive or negative; I
haven't modified any documentation as there's no point doing that if people
disagree with this approach.