[Bug target/83467] [7/8 Regression] ICE: in assign_by_spills, at lra-assigns.c:1476: unable to find a register to spill with -flive-range-shrinkage -m8bit-idiv
uros at gcc dot gnu.org
gcc-bugzilla@gcc.gnu.org
Thu Dec 21 20:49:00 GMT 2017
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83467
--- Comment #5 from uros at gcc dot gnu.org ---
Author: uros
Date: Thu Dec 21 20:48:34 2017
New Revision: 255956
URL: https://gcc.gnu.org/viewcvs?rev=255956&root=gcc&view=rev
Log:
PR target/83467
* config/i386/i386.md (*ashl<mode>3_mask): Add operand
constraints to operand 2.
(*<shift_insn><mode>3_mask): Ditto.
(*<rotate_insn><mode>3_mask): Ditto.
testsuite/ChangeLog:
PR target/83467
* gcc.target/i386/pr83467-1.c: New test.
* gcc.target/i386/pr83467-2.c: Ditto.
Added:
branches/gcc-7-branch/gcc/testsuite/gcc.target/i386/pr83467-1.c
branches/gcc-7-branch/gcc/testsuite/gcc.target/i386/pr83467-2.c
Modified:
branches/gcc-7-branch/gcc/ChangeLog
branches/gcc-7-branch/gcc/config/i386/i386.md
branches/gcc-7-branch/gcc/testsuite/ChangeLog
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