[Bug c/83402] New: PPC64 implementation of ./rs6000/emmintrin.h gives out of range for _mm_slli_epi32

[munroesj at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83402

            Bug ID: 83402
           Summary: PPC64 implementation of ./rs6000/emmintrin.h gives out
                    of range for _mm_slli_epi32
           Product: gcc
           Version: 8.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: c
          Assignee: unassigned at gcc dot gnu.org
          Reporter: munroesj at gcc dot gnu.org
  Target Milestone: ---

The rs6000/emmintrin.h implementation of _mm_slli_epi32 reports:
  error: argument 1 must be a 5-bit signed literal

For constant shift values > 15.

The implementation uses vec_splat_s32 (Vector Splat Immediate Signed Word) for
const shift values to generate the shift count for vec_vslw (Vector Shift Left
Word). This is preferred to the more expensive vec_splats.

The immediate field of vspltisw is 5 bits but it is sign extended and the shift
rang must be positive. This limits the immediate range for vspltisw to 0-15
(not the required 0-31).

The current implementation uses:

      if (__builtin_constant_p(__B))
        lshift = (__v4su) vec_splat_s32(__B);
      else
        lshift = vec_splats ((unsigned int) __B);

so we need something like:

      if (__builtin_constant_p(__B) && (__B < 16))