[Bug target/80108] ICE in aggregate_value_p at function.c:2028

[meissner at linux dot vnet.ibm.com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80108

--- Comment #11 from Michael Meissner <meissner at linux dot vnet.ibm.com> ---
On Fri, Mar 31, 2017 at 06:35:20PM +0000, kelvin at gcc dot gnu.org wrote:
> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80108
> 
> --- Comment #9 from kelvin at gcc dot gnu.org ---
> I've got a patch now that resolves this problem without creating regressions. 
> I'm attaching it for "discussion" here before I post for "official review".
> 
> Index: gcc/config/rs6000/rs6000.c
> ===================================================================
> --- gcc/config/rs6000/rs6000.c  (revision 246573)
> +++ gcc/config/rs6000/rs6000.c  (working copy)
> @@ -4273,8 +4273,30 @@ rs6000_option_override_internal (bool global_init_
>    /* For the newer switches (vsx, dfp, etc.) set some of the older options,
>       unless the user explicitly used the -mno-<option> to disable the code. 
> */
>    if (TARGET_P9_VECTOR || TARGET_MODULO || TARGET_P9_DFORM_SCALAR
> -      || TARGET_P9_DFORM_VECTOR || TARGET_P9_DFORM_BOTH > 0 ||
> TARGET_P9_MINMAX)
> +      || TARGET_P9_DFORM_VECTOR || TARGET_P9_DFORM_BOTH > 0)
>      rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~rs6000_isa_flags_explicit);
> +  else if (TARGET_P9_MINMAX)
> +    {
> +      if (have_cpu)
> +       {
> +         if (cpu_index == PROCESSOR_POWER9)
> +           /* legacy behavior: allow -mcpu-power9 with certain capabilities
> +              (eg -mno-vsx) explicitly disabled.  */

Note, -mpower9-minmax makes no sense without -mvsx, since it is a VSX
instruction.

It also requires upper reg support for the appropriate mode (i.e. double
requires TARGET_UPPER_REGS_DF and float requires TARGET_UPPER_REGS_SF, it is
probably simpler to require both).  This comes from a LRA behavior of crashing
if the constraint allows more registers than the register class allows.  We
could add additional constraints in the min/max insns if we wanted to support
no upper regs and min/max, but I don't think it is worth it.

(define_insn "*s<minmax><mode>3_vsx"
  [(set (match_operand:SFDF 0 "vsx_register_operand" "=<Ff>,<Fv>")
        (fp_minmax:SFDF (match_operand:SFDF 1 "vsx_register_operand"
"<Ff>,<Fv>")
                        (match_operand:SFDF 2 "vsx_register_operand"
"<Ff>,<Fv>")))]
  "TARGET_VSX && TARGET_<MODE>_FPR"
{
  return (TARGET_P9_MINMAX
          ? "xs<minmax>cdp %x0,%x1,%x2"
          : "xs<minmax>dp %x0,%x1,%x2");
}
  [(set_attr "type" "fp")])