[Bug target/41076] [avr] pessimal code for logical OR of 8-bit fields

[gjl at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=41076

--- Comment #8 from Georg-Johann Lay <gjl at gcc dot gnu.org> ---
Author: gjl
Date: Mon Nov 28 08:40:11 2016
New Revision: 242907

URL: https://gcc.gnu.org/viewcvs?rev=242907&root=gcc&view=rev
Log:
        PR 41076
        * config/avr/avr.md (SPLIT34): New mode iterator.
        (bitop): New code iterator.
        (*iorhi3.ashift8-*). New insn-and-split patterns.
        (*movhi): Post-reload split reg = 0.
        [!MOVW]: Post-reload split reg = reg.
        (*mov<mode>) [SI,SF,PSI,SQ,USQ,SA,USA]: Post-reload split reg = reg.
        (andhi3, andpsi3, andsi3): Post-reload split reg-reg operations.
        (iorhi3, iorpsi3, iorsi3): Same.
        (xorhi3, xorpsi3, xorsi3): Same.
        * config/avr/avr.c (avr_rtx_costs_1) [IOR && HImode]: Adjust rtx
        costs to *iorhi3.ashift8-* patterns.


Modified:
    trunk/gcc/ChangeLog
    trunk/gcc/config/avr/avr.c
    trunk/gcc/config/avr/avr.md