[Bug rtl-optimization/70164] [6 Regression] Code/performance regression due to poor register allocation on Cortex-M0

[law at redhat dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70164

--- Comment #12 from Jeffrey A. Law <law at redhat dot com> ---
Slight correction.  I was looking at the wrong part of the dump when I said
cse1 didn't change insn 28.  It is cse1 that changes insn 28.  So this is
strictly an issue with the transformations cse1 makes.