[Bug target/71191] aarch64 and others: __atomic_load;arithmetic;__atomic_compare_exchange loops should be able to generate better code with LL/SC-type constructs than a CAS loop

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71191

--- Comment #7 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
> On AArch64 there are restrictions on what kind of instructions can go into
> these LL/SC loops using the exclusive instructions i.e. the LDAXR / STLXR
> instructions. 

MIPS has a similar restriction.  I know one of AARCH64 (and MIPS) processor
which shows issues when some of those restrictions are violated (either load or
stores in-between the LL/SC).  I have seen now issues in LLVM and valgrind due
to that :).  So anything that makes LL and SC builtins I would to reject out
right.