[Bug target/64411] ICE: in verify_target_availability, at sel-sched.c:1577 with -Os -mcmodel=medium -fPIC -fschedule-insns -fselective-scheduling

[abel at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64411

--- Comment #2 from Andrey Belevantsev <abel at gcc dot gnu.org> ---
Created attachment 37432
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=37432&action=edit
patch

In this case, we get an inconsistency between the sched-deps interface, saying
we can't move an insn writing si register through a vector insn, and the
liveness analysis, saying we can.  The latter doesn't take into account
implicit_reg_pending_clobbers set calculated in sched-deps before register
allocation.  The solution is to reflect this set in our insn data
(sets/uses/clobbers).  An interesting thing would be to check what happens with
the register allocator if we'd actually moved one insn past the other.