[Bug tree-optimization/69282] [6 Regression] aarch64/armhf ICE on SPEC2006 464.h264ref at -O3

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69282

--- Comment #3 from Andrew Pinski <pinskia at gcc dot gnu.org> ---

  vector(4) <unnamed type> _6;
  vector(4) int vect_c_1.7;


  _6 = vect__5.5_1 != vect_cst__14;
  vect_c_1.7_2 = VEC_COND_EXPR <_6, vect_cst__15, { 1, 1, 1, 1 }>;


What I don't understand is why vectlowering is happening at all.  There should
be a vect select (BSL) which does this for aarch64 (there is one for aarch32
but I don't remember the mnemonic for it).