[Bug lto/69082] Final link fails on ARM using lto

[rearnsha at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69082

Richard Earnshaw <rearnsha at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|WAITING                     |NEW

--- Comment #9 from Richard Earnshaw <rearnsha at gcc dot gnu.org> ---
Confirmed.  

Looks like the bad instructions are generated somewhere during reload (lra).

Changing pseudo 18915 in operand 0 of insn 198 on equiv
[const(`*.LANCHOR0'+0x80
00)]
      Creating newreg=102333, assigning class CORE_REGS to addr r102333
           Change to class GENERAL_REGS for r102333
            0 Non-pseudo reload: reject+=2
            0 Non input pseudo reload: reject++
            0 Early clobber: reject++
            1 Matching earlyclobber alt: reject--
            1 Dying matched operand reload: reject++
            2 Non-pseudo reload: reject+=2
            2 Non input pseudo reload: reject++
          alt=0,overall=19,losers=2,rld_nregs=6
            0 Non-pseudo reload: reject+=2
            0 Non input pseudo reload: reject++
            0 Early clobber: reject++
            1 Matching earlyclobber alt: reject--
            1 Dying matched operand reload: reject++
            2 Matching earlyclobber alt: reject--
            alt=1: Bad operand -- refuse
            0 Non-pseudo reload: reject+=2
            0 Non input pseudo reload: reject++
            0 Early clobber: reject++
            2 Non-pseudo reload: reject+=2
            2 Non input pseudo reload: reject++
          alt=2,overall=19,losers=2,rld_nregs=4
            0 Non-pseudo reload: reject+=2
            0 Non input pseudo reload: reject++
            0 Early clobber: reject++
            1 Matching earlyclobber alt: reject--
            1 Dying matched operand reload: reject++
          alt=3,overall=10,losers=1,rld_nregs=4
            0 Non-pseudo reload: reject+=2
            0 Non input pseudo reload: reject++
            0 Early clobber: reject++
          alt=4,overall=10,losers=1,rld_nregs=2
            0 Non-pseudo reload: reject+=2
            0 Non input pseudo reload: reject++
            0 Early clobber: reject++
            1 Matching earlyclobber alt: reject--
            1 Non-pseudo reload: reject+=2
            1 Non input pseudo reload: reject++
            alt=0,overall=18,losers=2 -- refuse
            0 Non-pseudo reload: reject+=2
            0 Non input pseudo reload: reject++
            0 Early clobber: reject++
            1 Matching earlyclobber alt: reject--
            1 Non-pseudo reload: reject+=2
            1 Non input pseudo reload: reject++
            alt=1,overall=18,losers=2 -- refuse
            0 Non-pseudo reload: reject+=2
            0 Non input pseudo reload: reject++
            0 Early clobber: reject++
            1 Non-pseudo reload: reject+=2
            1 Non input pseudo reload: reject++
            alt=2,overall=19,losers=2 -- refuse
            0 Non-pseudo reload: reject+=2
            0 Non input pseudo reload: reject++
            0 Early clobber: reject++
            1 Matching earlyclobber alt: reject--
            1 Non-pseudo reload: reject+=2
            1 Non input pseudo reload: reject++
            alt=3,overall=18,losers=2 -- refuse
            0 Non-pseudo reload: reject+=2
            0 Non input pseudo reload: reject++
            0 Early clobber: reject++
            1 Non-pseudo reload: reject+=2
            1 Non input pseudo reload: reject++
            alt=4,overall=19,losers=2 -- refuse
         Choosing alt 4 in insn 198:  (0) &r  (1) r  (2) Dd {*arm_adddi3}
      Creating newreg=102334, assigning class GENERAL_REGS to r102334
  198: {r102334:DI=r18916:DI+0x1;clobber cc:CC;}
      REG_DEAD r18916:DI
      REG_EQUIV [r88543:SI]
    Inserting insn reload before:
 125176: r102333:SI=high(const(`*.LANCHOR0'+0x8000))
 125177: r102333:SI=r102333:SI+low(const(`*.LANCHOR0'+0x8000))

Oops, those reload insns aren't valid!