[Bug target/69773] gcc ICE at -O2 and above on valid code on x86_64-linux-gnu in "assign_by_spills"

rguenth at gcc dot gnu.org gcc-bugzilla@gcc.gnu.org
Fri Feb 12 08:33:00 GMT 2016


https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69773

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Keywords|                            |ra
             Target|                            |x86_64-*-*, i?86-*-*
             Status|UNCONFIRMED                 |NEW
   Last reconfirmed|                            |2016-02-12
                 CC|                            |uros at gcc dot gnu.org,
                   |                            |vmakarov at gcc dot gnu.org
          Component|tree-optimization           |target
     Ever confirmed|0                           |1

--- Comment #1 from Richard Biener <rguenth at gcc dot gnu.org> ---
With 4.7 reload fails in a similar way:

t.i:12:1: error: unable to find a register to spill in class ‘DREG’
t.i:12:1: error: this is the insn:
(insn 8 7 9 2 (parallel [
            (set (reg:SI 2 cx [64])
                (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 4 si
[orig:65 p1_1(D)->k ] [65]))
                            (sign_extend:DI (reg:SI 2 cx [67])))
                        (const_int 32 [0x20]))))
            (clobber (scratch:SI))
            (clobber (reg:CC 17 flags))
        ]) t.i:8 334 {*smulsi3_highpart_1}
     (expr_list:REG_DEAD (reg:SI 2 cx [67])
        (expr_list:REG_UNUSED (reg:CC 17 flags)
            (expr_list:REG_EQUAL (truncate:SI (lshiftrt:DI (mult:DI
(sign_extend:DI (reg:SI 4 si [orig:65 p1_1(D)->k ] [65]))
                            (const_int 1374389535 [0x51eb851f]))
                        (const_int 32 [0x20])))
                (nil)))))
t.i:12:1: internal compiler error: in spill_failure, at reload1.c:2120


I think you are simply unlucky in using dx as a fixed register as that's a
special one for the division instruction.


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