[Bug target/67260] [sh] Register spill bug for sibcall+complex+softfloat

[amonakov at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67260

--- Comment #2 from Alexander Monakov <amonakov at gcc dot gnu.org> ---
(added SH maintainers, Oleg Endo and Kaz Kojima to Cc)

In response to the last sentence in my analysis, on IRC Rich pointed out that
using r1/r2/r3 should be better that r0 because some instruction can operate
only on r0 so that would constrain scheduling.