[Bug target/69667] [6 Regression] ppc64le -mlra: ICE: Max. number of generated reload insns per insn is achieved (90)

[meissner at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69667

Michael Meissner <meissner at gcc dot gnu.org> changed:

           What    |Removed                     |Added
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             Status|NEW                         |ASSIGNED
           Assignee|unassigned at gcc dot gnu.org      |meissner at gcc dot gnu.org

--- Comment #7 from Michael Meissner <meissner at gcc dot gnu.org> ---
The error is LRA requires that every register that a constraint targets be a
valid register for the mode.  In this case, the 3 move insns that target TFmode
(i.e. long double using the 128-bit IBM extended double format) were using 'ws'
and 'wm' constraints.  On power8 systems can match all of the VSX registers by
default.  However TFmode/IFmode is restricted to being in the traditional
floating point registers.  Reload did not have a problem if some of the
registers mapped by the constraint were unavailable for a given mode, but LRA
doesn't like it.