[Bug rtl-optimization/67609] [5 Regression] Generates wrong code for SSE2 _mm_load_pd

[ubizjak at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67609

--- Comment #44 from Uroš Bizjak <ubizjak at gmail dot com> ---
(In reply to rsandifo@gcc.gnu.org from comment #43)
> FWIW, the proposed patch for PR69577 fixes this testcase
> with the aarch64_cannot_change_mode_class change reverted.
> The code quality looks slightly better too.

The same is true with x86_64. Following revert causes no testsuite regressions:

--cut here--
Index: config/i386/i386.c
===================================================================
--- config/i386/i386.c  (revision 233079)
+++ config/i386/i386.c  (working copy)
@@ -43283,25 +43283,12 @@ ix86_cannot_change_mode_class (machine_mode from,

   if (MAYBE_SSE_CLASS_P (regclass) || MAYBE_MMX_CLASS_P (regclass))
     {
-      int from_size = GET_MODE_SIZE (from);
-      int to_size = GET_MODE_SIZE (to);
-
       /* Vector registers do not support QI or HImode loads.  If we don't
         disallow a change to these modes, reload will assume it's ok to
         drop the subreg from (subreg:SI (reg:HI 100) 0).  This affects
         the vec_dupv4hi pattern.  */
-      if (from_size < 4)
+      if (GET_MODE_SIZE (from) < 4)
        return true;
-
-      /* Further, we cannot allow word_mode subregs of full vector modes.
-         Otherwise the middle-end will assume it's ok to store to
-         (subreg:DI (reg:TI 100) 0) in order to modify only the low 64 bits
-         of the 128-bit register.  However, after reload the subreg will
-         be dropped leaving a plain DImode store.  This is indistinguishable
-         from a "normal" DImode move, and so we're justified to use movsd,
-         which modifies the entire 128-bit register.  */
-      if (to_size == UNITS_PER_WORD && from_size > UNITS_PER_WORD)
-       return true;
     }

   return false;
--cut here--