[Bug target/78516] [7 Regression] ICE in lra_assign for e500v2

[vmakarov at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78516

--- Comment #10 from Vladimir Makarov <vmakarov at gcc dot gnu.org> ---
(In reply to Peter Bergner from comment #8)

> where "src" is the subreg:SI ..., so the new_reg mode will be SImode and we
> then replace the whole SET_SRC (curr_insn_set) which is the subreg:SI
> (reg:DF ...) which doesn't seem correct.
> 
> Vlad, should we have never got this far into check_and_process_move() with
> this type of insn?  Adding an ugly hack that creates an early out for this
> insn (ie, set (reg:SI) (subreg:SI (reg:DF))) seems to make us compile.
> 

I believe we should process this insn in check_and_process_move.  It is the
single place to check secondary reload hooks and insns.

> If we are supposed to still process this insn, then how about something like
> the following patch that creates a new_reg with the mode of the src register
> and not the subreg and then replacing that instead of the entire subreg src?
> This too eliminates the SEGV/ICE.

I think creating a new reg from the register instead of the sub-register is
safer.  Also it results in a better code too, if the subregister is a
paradoxical one,  So the patch idea is right.  But I believe it is not
finished.  I am attaching a new version of the patch.  If it is ok, I can
commit it after your confirmation.