[Bug target/67609] [5/6 Regression] Generates wrong code for SSE2 _mm_load_pd

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67609

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Target|                            |x86_64-*-*
             Status|UNCONFIRMED                 |NEW
      Known to work|                            |4.9.3
           Keywords|                            |ra, wrong-code
   Last reconfirmed|                            |2015-09-17
          Component|regression                  |target
                 CC|                            |uros at gcc dot gnu.org,
                   |                            |vmakarov at gcc dot gnu.org
     Ever confirmed|0                           |1
            Summary|[Regression] Generates      |[5/6 Regression] Generates
                   |wrong code for SSE2         |wrong code for SSE2
                   |_mm_load_pd                 |_mm_load_pd
   Target Milestone|---                         |5.3

--- Comment #2 from Richard Biener <rguenth at gcc dot gnu.org> ---
;; MEM[(__m128d * {ref-all})&v] = reg.0_2;

(insn 6 5 0 (set (reg/v:TI 90 [ v ])
        (mem/c:TI (symbol_ref:DI ("reg") [flags 0x2]  <var_decl 0x7fba2a03eb40
reg>) [0 reg+0 S16 A128]))
/abuild/rguenther/trunk-g/gcc/include/emmintrin.h:161 -1
     (nil))


;; v[0] = b_4(D);

(insn 7 6 0 (set (subreg:DF (reg/v:TI 90 [ v ]) 0)
        (reg/v:DF 88 [ b ])) t.c:7 -1
     (nil))

;; reg = _6;

(insn 8 7 0 (set (mem/c:V2DF (symbol_ref:DI ("reg") [flags 0x2]  <var_decl
0x7fba2a03eb40 reg>) [0 reg+0 S16 A128])
        (subreg:V2DF (reg/v:TI 90 [ v ]) 0)) t.c:8 -1
     (nil))

the subreg set is expected to preserve the upper part.  It later gets
later assigned *movdf_internal - so eventually we'd have expected
a lowpart instead.  Not sure about bigger-than wordmode regs and subregs...

GCC 4.9 and before go through the stack extensively (otherwise identical
GIMPLE IL and RTL expansion though).  So it looks like a backend
(pattern constraints?) or RA related bug (the issue appears after IRA/reload).