[Bug target/64342] [5 Regression] Tests failing when compiled with '-m32 -fpic' after r216154.

[law at redhat dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64342

Jeffrey A. Law <law at redhat dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |law at redhat dot com
           Assignee|unassigned at gcc dot gnu.org      |vmakarov at redhat dot com

--- Comment #13 from Jeffrey A. Law <law at redhat dot com> ---
AFACIT only one issue is left, namely avx512f-kandnw-1.c when compiled with
-mavx512f -m32 does not generate a kandnw instruction.

This appears to be some kind of register allocation issue.

In the IRA dump we have:

ssigning 69 to a1r105
Assigning 70 to a5r103
Assigning 69 to a6r101
Disposition:
   10:r87  l0     0    3:r91  l0    22    4:r92  l0    23    2:r93  l0    21
    9:r100 l0    21    6:r101 l0    69    8:r102 l0     0    5:r103 l0    70
    7:r104 l0     1    1:r105 l0    69    0:r110 l0    21

Which is basically what we want for insn 17 to generate the proper insn:

(insn 17 11 19 2 (parallel [
            (set (reg:HI 105)
                (and:HI (not:HI (reg:HI 101 [ k1 ]))
                    (reg:HI 103 [ k2 ])))
            (clobber (reg:CC 17 flags))
        ]) ./include/avx512fintrin.h:9995 388 {kandnhi}
     (expr_list:REG_DEAD (reg:HI 103 [ k2 ])
        (expr_list:REG_DEAD (reg:HI 101 [ k1 ])
            (expr_list:REG_UNUSED (reg:CC 17 flags)
                (nil)))))

LRA comes along and mucks things up.  It seems to initially do the right thing:

         Choosing alt 2 in insn 17:  (0) !k  (1) k  (2) k {kandnhi}


Then later:

********** Assignment #1: **********

    Spill r101 after risky transformations
         Assigning to 117 (cl=MASK_EVEX_REGS, orig=105, freq=2000, tfirst=117,
tfreq=2000)...
           Assign 71 to reload r117 (freq=2000)
  Reassigning non-reload pseudos
           Assign 0 to r101 (freq=2000)

Note the Assign 0 to r101, at this point we're going to lose badly.

         Choosing alt 1 in insn 17:  (0) &r  (1) 0  (2) r {kandnhi}
      Creating newreg=118 from oldreg=105, assigning class GENERAL_REGS to r118
      Creating newreg=119 from oldreg=103, assigning class GENERAL_REGS to r119

With insn 17 looking like:

(insn 17 40 39 2 (parallel [
            (set (reg:HI 0 ax [105])
                (and:HI (not:HI (reg:HI 0 ax [105]))
                    (reg:HI 2 cx [orig:103 k2 ] [103])))
            (clobber (reg:CC 17 flags))
        ]) ./include/avx512fintrin.h:9995 388 {kandnhi}
     (nil))

with input & output reloads to get things into the k registers and of course no
kandnw instruction since we end up doing the logical operation in the general
purpose registers.