[Bug rtl-optimization/64317] [5 Regression] Ineffective allocation of PIC base register
law at redhat dot com
gcc-bugzilla@gcc.gnu.org
Tue Mar 3 22:39:00 GMT 2015
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64317
--- Comment #19 from Jeffrey A. Law <law at redhat dot com> ---
Making reload_cse_regs less pessimistic at CODE_LABELs really isn't feasible.
cselib isn't easily turned into a scoped hash table and the multiple assignment
nature of RTL means that a simple scoped hash table isn't sufficient anyway.
I'm currently poking at postreload-gcse. The basic idea being to detect when
an occurrence is transparent through a block and an occurrence exists in the
block's one and only predecessor. In that case pretend the occurrence also
exists at the end of the current block. I don't expect this to occur often,
thus I'm not computing transparency for each expression in all blocks and doing
a traditional dataflow propagation.
With that special case in place, I get just 5 reloads of the PIC register,
which appears minimal given the other register allocation decisions. I need to
ponder a couple implementation details, but this may be the final resolution to
this BZ :-)
More information about the Gcc-bugs
mailing list