[Bug rtl-optimization/66412] [5/6 Regression] ICE on valid code at -O2 and -O3 with -g enabled in simplify_subreg, at simplify-rtx.c:5748

[ubizjak at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66412

--- Comment #3 from Uroš Bizjak <ubizjak at gmail dot com> ---
This testcase exposes latent problem in combine pass in conjunction with debug.

We start with:

[...]

(insn 8 7 9 2 (set (reg:QI 95)
        (eq:QI (reg:CCZ 17 flags)
            (const_int 0 [0]))) pr66412.c:9 597 {*setcc_qi}
     (expr_list:REG_DEAD (reg:CCZ 17 flags)
        (nil)))
(insn 9 8 11 2 (set (reg:SI 94 [ D.1784 ])
        (zero_extend:SI (reg:QI 95))) pr66412.c:9 134 {*zero_extendqisi2}
     (expr_list:REG_DEAD (reg:QI 95)
        (nil)))
(debug_insn 11 9 12 2 (var_location:HI g (subreg:HI (reg:SI 94 [ D.1784 ]) 0))
pr66412.c:9 -1
     (nil))
(debug_insn 12 11 13 2 (var_location:HI e (subreg:HI (ashift:SI (reg:SI 94 [
D.1784 ])
            (const_int 1 [0x1])) 0)) pr66412.c:10 -1
     (nil))
(insn 13 12 14 2 (parallel [
            (set (reg:SI 96 [ D.1783 ])
                (ashift:SI (reg:SI 94 [ D.1784 ])
                    (const_int 1 [0x1])))
            (clobber (reg:CC 17 flags))
        ]) pr66412.c:11 501 {*ashlsi3_1}
     (expr_list:REG_DEAD (reg:SI 94 [ D.1784 ])
        (expr_list:REG_UNUSED (reg:CC 17 flags)
            (nil))))
(insn 14 13 15 2 (set (reg:CCZ 17 flags)
        (compare:CCZ (subreg:HI (reg:SI 96 [ D.1783 ]) 0)
            (const_int 0 [0]))) pr66412.c:11 2 {*cmphi_ccno_1}
     (expr_list:REG_DEAD (reg:SI 96 [ D.1783 ])
        (nil)))
(insn 15 14 16 2 (set (reg:QI 98)
        (ne:QI (reg:CCZ 17 flags)
            (const_int 0 [0]))) pr66412.c:11 597 {*setcc_qi}
     (expr_list:REG_DEAD (reg:CCZ 17 flags)
        (nil)))

[...]

and combine pass sequentially combines several insns into (insn 15):

Trying 8 -> 9:
Successfully matched this instruction:
(set (reg:SI 94 [ D.1784 ])
    (eq:SI (reg:CCZ 17 flags)
        (const_int 0 [0])))
allowing combination of insns 8 and 9
original costs 4 + 4 = 8
replacement cost 4
deferring deletion of insn with uid = 8.
modifying insn i3     9: r94:SI=flags:CCZ==0
      REG_DEAD flags:CCZ
deferring rescan insn with uid = 9.

Trying 13 -> 14:
Successfully matched this instruction:
(set (reg:CCZ 17 flags)
    (compare:CCZ (ashift:SI (reg:SI 94 [ D.1784 ])
            (const_int 1 [0x1]))
        (const_int 0 [0])))
allowing combination of insns 13 and 14
original costs 4 + 4 = 8
replacement cost 4
deferring deletion of insn with uid = 13.
modifying insn i3    14: {flags:CCZ=cmp(r94:SI<<0x1,0);clobber scratch;}
      REG_DEAD r94:SI
deferring rescan insn with uid = 14.

Trying 9, 14 -> 15:
Failed to match this instruction:
(set (reg:QI 98)
    (ne:QI (eq:SI (reg:CCZ 17 flags)
            (const_int 0 [0]))
        (const_int 0 [0])))
Splitting with gen_split_5441
Successfully matched this instruction:
(set (reg:QI 98)
    (eq:QI (reg:CCZ 17 flags)
        (const_int 0 [0])))
allowing combination of insns 9, 14 and 15
original costs 4 + 4 + 4 = 12
replacement cost 4
deferring deletion of insn with uid = 14.

Calling propagate_for_debug for:

(debug_insn 11 9 12 2 (var_location:HI g (subreg:HI (reg:SI 94 [ D.1784 ]) 0))
pr66412.c:9 -1
     (nil))

we found (wrong) replacement for (reg:SI 94):

(eq:QI (reg:CCZ 17 flags)
    (const_int 0 [0]))

and we try to call simplify_gen_subreg with:

(gdb) f 3
#3  0x0000000000aa2aaa in simplify_gen_subreg (outermode=HImode,
op=0x7ffff12aff00, innermode=SImode, byte=0) at
/home/uros/gcc-svn/trunk/gcc/simplify-rtx.c:5969
5969      newx = simplify_subreg (outermode, op, innermode, byte);
(gdb) p debug_rtx (op)
(eq:QI (reg:CCZ 17 flags)
    (const_int 0 [0]))

which crashes at:

#2  0x0000000000aa261a in simplify_subreg (outermode=HImode, op=0x7ffff12aff00,
innermode=SImode, byte=0) at /home/uros/gcc-svn/trunk/gcc/simplify-rtx.c:5749
5749      gcc_assert (GET_MODE (op) == innermode